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Panel Level Packaging
Panel Level Packaging
In this paper a wide variety of technologies are described that allow the generation of maximum miniaturized microsystems or SiPs.
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Authored By:
R. Aschenbrenner, K.F. Becker, T. Braun, and A. Ostmann
Fraunhofer Institute for Reliability and Microintegration
Berlin, Germany
,{url:'http://www.circuitinsight.com/videos/programs_final.mp4'}], clip:{autoBuffering:true, autoPlay:true, scaling:'scale' } }).ipad();
Developing demands and the market show two main trends helping to shape the ongoing development of system integration technologies. First of all is an ongoing increase in the number of functions directly included in a system - such as electrical, optical, mechanical, biological and chemical processes - combined with the demand for higher reliability and longer system lifetime. Second is the increasingly seamless merging of products and electronics, which necessitates adapting electronics to predefined materials, forms and application environments. Only by these means systems sensors - which are often installed in extremely harsh environments - and signal processing can be implemented near to the point where signals are occurring.

Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-inPolymer)are two major packaging trends in this area. This paper describes the potential of heterogeneous integration technologies researched at Fraunhofer IZM with a strong focus on embedding in printed circuit boards and embedding in molded reconfigured wafers with an outlook of advanced large area encapsulation processes for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing.

Heterogeneous integration bridges the gap between microelectronics and its derived applications. Two main forces drive progress in this area - emerging device technologies and new application requirements. New technologies and architectures are arising to bring the progress made in microelectronics, microsystem technologies, and bio-electronic or photonic component technologies into application. The future belongs to integration technologies that combine several components into a highly integrated assembly in one package.

One target application was a multi sensor device for indoor navigation purposes integrating magnetic sensors, an acceleration sensor and a pressure sensor - based on sensor development within the MST-SmartSense project. For demonstration purposes the wafer level approach has been applied to pressure sensor / ASIC and to acceleration sensor combinations. For each combination the best suited technology variant was chosen and package stacking could be demonstrated. Successful functional testing of this stacked device also proofs that this packaging technology is suited for stress sensitive sensor ICs.

Apart from showing the overall suitability of embedding technology the special focus was put on z-axis routing possibilities, where through mold vias have been evaluated regarding process and reliability.

In this paper a wide variety of technologies has been described that allow the generation of maximum miniaturized microsystems or SiPs, consisting of at least two components - all technologies bear the possibility to integrate multiple heterogeneous components, fulfilling this demand to heterogeneous integration.
Initially Published in the SMTA Proceedings
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