Electronics Assembly Knowledge, Vision & Wisdom
Three Dimensional Integration Focusing on Device Embedded Substrate
Three Dimensional Integration Focusing on Device Embedded Substrate
In this paper, EDA tools, TEG chips, and several evaluation equipment developed in Fukuoka are explained.
Materials Tech

Authored By:
Hajime Tomokage
Department of Electronics Engineering and Computer Science
Fukuoka University, Fukuoka, Japan
,{url:'http://www.circuitinsight.com/videos/programs_final.mp4'}], clip:{autoBuffering:true, autoPlay:true, scaling:'scale' } }).ipad();
Summary
The national research project on 3D integration technology had been carried on in Fukuoka, Japan from 2002 to 2012. The system-in-a-package (SiP) design tools STEERSIP and STEERMEMS, test element group (TEG) chips for evaluating the assembling process, and the evaluation equipment such as scanning electron and laser beams induced current (SELBIC) measurement system have been developed. In 2011, a new research center for 3D semiconductors was constructed, where the main research is on device embedded substrate and silicon interposer with through silicon via (TSV).

According to the Japan Electronics Packaging and Circuits Association (JPCA) standard on device embedded substrate EB01 and EB02, the evaluation kits for device embedded substrate are developed in order for device companies to perform function test of embedded devices with the common substrate structure.
Initially Published in the SMTA Proceedings
Submit A Comment

Comments are reviewed prior to posting. Please avoid discussion of pricing or recommendations for specific products. You must include your full name to have your comments posted. We will not post your email address.

Your Name


Company


E-mail


Country


Comments


Authentication

Please type the number displayed into the box. If you receive an error, you may need to refresh the page and resubmit the information.



Related Programs
bullet Miniaturization of Hearing Aid Electronics Using Embedded Die Packaging
bullet Status and Outlooks of Flip Chip Technology
bullet Multilayer Ceramic Capacitors: Mitigating Rising Failure Rates
bullet Three Dimensional Integration Focusing on Device Embedded Substrate
bullet Leadless Flip Chip PLGA for Networking Applications
bullet New Approaches to Develop a Scalable 3D IC Assembly Method
bullet Flip Chip LED Solder Assembly
bullet 3D IC Integration Technology Development in China
bullet Fine Pitch CU Pillar with Bond on Lead Assembly Challenges for High Performance Flip Chip Package
bullet Failure Modes in Wire Bonded and Flip Chip Packages
More Related Programs