Electronics Assembly Knowledge, Vision & Wisdom
Simulation of Embedded Component
Simulation of Embedded Component
Embedded components technology has launched its implementation in volume products demanding for highest miniaturization level.
Analysis Lab

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Corrosion, Contamination, Data Acquisition, ESD and EOS, Inspection, Measurement, Profiling, Reliability, R&D, RFID, Solder Defects, Test, Tombstoning, X-ray and more.
Authored By:
J. Stahr, M. Morianz
AT&S, Leoben, Austria

M. Brizoux, A. Grivon, W. Maia
Thales Global Services, Meudon-la-Foret, France

Embedded components technology has launched its implementation in volume products demanding for highest miniaturization level. Small modules with embedded dies and passive components on the top side are mounted in hand held devices. Smart phones are the enablers for this new technology using the capabilities of embedded components. These modules have already shown a high level of reliability which has been a prerequisite to get acceptance for volume products. Embedded dies are relative small with dimensions of about two by two millimeter and therefore all critical topics like the CTE mismatch of components and PCB materials, process die attachment are on a non-critical level.

The road maps for the application development show a drastic increase of the complexity of the modules and in parallel increasing I/O numbers and die dimensions. Applications in the development pipeline show already die dimensions of seven by seven millimeter.

Based on this development roadmap a simulation project was started with the Material Center Leoben and Thales Global Services to evaluate the stress situation of embedded components and to build a thermo-mechanical simulation model. The verification of this model was started by characterization of silicon dies and embedding of standardized components into PCB to get detailed stress parameters for these components. The next step of simulation deals with the simulation of embedding processes. Die assembly is the first process followed by the lamination process to form the embedded core.

For the assembly process a DOE has been done to correlate the results with the simulation model. All along the European funded FP7 HERMES project huge efforts have been deployed in order to characterize the reliability of active and passive embedded chips, as well as packages assembled on the outer layers of the PCB. To achieve a high level of reliability of future complex modules using HERMES technology, work has been done to address different aspects like process optimization including different build-ups, best choice of base material, different size of active dice and design rules, knowledge of failure mode.

Chip embedding technology is currently used in high volume production for miniaturized modules used in smartphones, and is trying to extend to higher complexity devices with larger die sizes. For complex embedded systems, thermo-mechanical concerns increase and needs to be managed. In this paper, it has been shown that a FEM simulation approach has been developed to identify high stress areas and the deformation fields within an embedded package.

The model can be used to simulate the thermo-mechanical stresses seen by embedded components at different PCB manufacturing stages, in particular during lamination which is the most critical. A complementary experimental test program using a large number of build-up configurations has also been conducted to analyze the incidence of the PCB structure and constitution on the solder joint reliability of BGA/QFN components.

Among the results, the study highlighted that for 1.0mm-pitch BGAs the effect of resin-content was insignificant and the effects of the base material and the PCB thickness were relatively small. By contrast, the influence of those parameters on assembled QFN components is significant, the total resin-content of the board being the most important parameter. Further analysis on a more complex PCB architecture will be presented to show the impact of embedded dies on the reliability of overlapping soldered BGA/QFN packages.

Initially Published in the IPC Proceedings

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