Electronics Assembly Knowledge, Vision & Wisdom
Last Will and Testament of the BGA Void
Last Will and Testament of the BGA Void
This paper investigates the impact of voids in BGA and CSP components using thermal cycle testing per the IPC specification for tin-lead solder alloys.
Analysis Lab

Authored By:
David Hillman, Dave Adams, Tim Pearson, Brad Williams, Brittany Petrick, and Ross Wilcoxon
Rockwell Collins, Cedar Rapids, IA, USA

David Bernard, Ph.D., John Travis, Evstatin Krastev, Ph.D., and Vineeth Bastin
Nordson DAGE, Fremont, CA, USA
,{url:'http://www.circuitinsight.com/videos/last_will_testament_bga_void.mp4'},{url:'http://www.circuitinsight.com/videos/programs_final.mp4'}], clip:{autoBuffering:true, autoPlay:true, scaling:'scale' } }).ipad();
Transcript
The impact of voiding on the solder joint integrity of BGAs and CSPs can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location or geometry configurations.

These investigations have focused on thermal cycle testing at 0C-100C, which is typically used to evaluate commercial electronic products.

This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing in accordance with the IPC specification for tin-lead solder alloys. A proposed BGA void requirement revision is extracted from the results analysis.
Summary
The impact of voiding on the solder joint integrity of ball grid arrays (BGAs)/chip scale packages (CSPs) can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location/geometry configurations. These investigations have focused on thermal cycle testing at 0°C-100°C, which is typically used to evaluate commercial electronic products.

This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing (-55°C to +125°C) in accordance with the IPC-9701 specification for tin/lead solder alloys. This temperature range is more typical of military and other high performance product use environments. A proposed BGA void requirement revision for the IPC-JSTD-001 specification will be extracted from the results analysis.
Conclusions
The Coyle investigation found that macro voids reduce solder joint reliability by reducing the effective attachment area and that this geometric effect was independent of solder alloy composition. The study concluded that the dominant factor that impacts solder joint integrity was void location and not the void size or density of voids.
Initially Published in the SMTA Proceedings
Submit A Comment

Comments are reviewed prior to posting. Please avoid discussion of pricing or recommendations for specific products. You must include your full name to have your comments posted. We will not post your email address.

Your Name


Company


E-mail


Country


Comments





Related Programs
bullet Cause of Unusual Contamination?
bullet Is There a Passive Component Solder Void Limit?
bullet What is Causing Solder Joint Cracking?
bullet Causes of PCB Delamination
bullet Effects of Tin and Copper on Tin Whisker Formation
bullet Impact of Dust on PCB Assembly Reliability
bullet Collaboration to Combat Head on Pillowing Defects
bullet The Effects of Flux Residues on Reliability
bullet Tombstone Chip Caps Revisited
bullet Cause of Cracking on SOT23 Components
More Related Programs
About | Advertising | Contact | Directory | Directory Search | Directory Submit | Privacy | Programs | Program Search | Sponsorship | Subscribe | Terms

Circuit Insight
6 Liberty Square #2040, Boston MA 02109 USA

Jeff Ferry, Publisher | Ken Cavallaro, Editor/Business Manager

Copyright © Circuitnet LLC. All rights reserved.
A Circuitnet Media Publication