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How to Reduce Voiding on QFN Components

How to Reduce Voiding on QFN Components
I'm concerned about voiding in the central ground planes of my QFN components. What can I do and how concerned should I be?
Board Talk


Welcome to Board Talk with Jim Hall and Phil Zarrow, the Assembly Brothers here at Board Talk, but by day going as ITM Consulting. And let's look at what kind of question we have today.

J.R. writes, "I'm getting concerned about voiding in the central ground planes of my QFN components. What can I do about that and how concerned should I be about it?"

First of all I want to say that although many of the components we deal with technically are QFNs, the new IPC term is BTC, Bottom Terminated Components.

So on these bottom terminated leadless components, sometimes known as QFNs, voiding issues have been around for a while. One question is how much voiding is actually permissible.That's defined by the conductivity and as well as the mechanical strength. We've seen cases where 65% voiding is permitted. 

But if you want to try to reduce voiding there are a number of different methods. One methodology is the use of preforms. Indium Corporation has some excellent papers on this. The flux is on the outside of the preform, as opposed to mixed in with the solder paste in normal solder paste.


What does a preform look like? 

The preforms we're talking about not the old-fashioned donuts we used to remember. These are basically solder slugs and they are introduced on tape in real and put down by the pick and place machines.

So it's a rectangular square piece of solid solder about the size or slightly smaller than the pad with flux on the outside.

So the flux has less chance to get entrapped as it might in solder paste. So that's a method worth experimenting with. Your result may vary, but it's well worth a try.

There are an infinite number of variations of the window pane technique where you print solder paste on less than a 100 percent of the area using some pattern of apertures within the standard within the area of the pad. That's a whole day's work, perhaps we will talk about that another day.

So thanks for listening. And whether you're soldering bottom terminated leadless components or big half-watt resistors, whatever you do ...

Don't solder like my brother.

Please don't solder like my brother.


Lets not forget the interaction of the metallurgy involved here either.

Immersion gold PCBs will increase voiding particularly when used with some Lead Free solder pastes. This can be improved by using electroflash gold, or better yet convert to matte tin or silver finishes to reduce the variety of metals involved in the connection.

My experimentation has shown the Immersion gold finish makes it a challenge to do better than 50% void even with very good 12 zone reflow profiles.

Bruce Webster, Iridium Communications
Please visit this site for a new alternative:
Matt Kelly, IBM Corporation
In addition to electrical and mechanical reasons for limiting the amount of voiding, also need to consider how much voiding affects thermal conductivity for higher power applications.
Derek Vanditmars, Delta Controls
You talked about "How to Reduce Voiding on QFN Components, BTC. However, no comparison samples provided.
Victor G. Hernandez, Dell inc., USA
This is our longtime experience with good soldering results concerning central ground planes and exposed pads for QFNs/BTCs.

On design level we take:
  • for the copper pad: a 1:1 relation between the size of the central pad of the component and the pad size (X, Y)
  • for the solder paste : the 49% rule : size is (X * 0.70, Y * 0.70), centered within the copper pad.
For sizes > 4mm we draw manually solder paste dots in a way the total amount of solder paste is about 49% of the total copper pad area.

Take e.g. 1.4mm solder paste each 2.0mm Cu. Like this the flux fumes can easily get away.

Please don't put through hole via's inside such pads : control is lost over the amount of solder left, and, the other PCB side is getting influenced. Apply by preference copper filled microvias.
Patrick Hendrickx, Septentrio Satellite Navigation, Belgium
At a SMT table top show I attended in Austin, there was a talk about QFN/BTC components. Their rule was small holes in the ground plane and about 50% solder coverage. This became the 25% rule that we use. A strip 25% of the width and length of the ground pad is removed leaving a 4 pane solder pattern that is about 57% of the area. It works great for us in both leaded and lead-free solder applications.
Will Dauchy, Suntronic, Inc, USA

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