Virtual Access Augments Test Coverage



Virtual Access Augments Test Coverage
Detecting open solder connections with electrical test techniques is a major challenge for manufacturers because of the erosion of test pads.
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Authored By:


Anthony J. Suto
Teradyne Inc.
North Reading, MA, USA

Transcript


Detecting open solder connections on PCB assemblies with electrical test techniques is a major challenge for manufacturers of today's computing, networking, communications and RF printed circuit boards; primarily because of the erosion of test pads on these products.

There are several factors behind this - the first involves the increase in the PCB component I/O and wiring densities, and the second is the increase in signaling speed on circuit board traces.

Traditional boundary scan is one possible solution to the lack of test pads on these products.

Boundary scan compliant devices utilize built-in testability structures on the input and output device pins for the purpose of stimulating and capturing on-board signals that can identify typical process defects, including open and shorted connections.

Boundary scan devices that are interconnected to other scan devices can readily be tested for connectivity defects, but often times a boundary scan part connects to a socket or a connector that is vacant during the time that the assembly is being tested.  

These board interconnect scenarios require a different test method to regain fault coverage and pin level diagnostics.

Vectorless test is a capacitive based sensing technology whereby a node on the board is excited by a low level sinusoidal signal and a capacitive sensor plate is placed proximate to the IC, socket or connector that is being interrogated for connectivity defects.

This technique compares the measured signal amplitude against pre-determined test limits to determine whether there is an electrical connection to the device.

Vectorless test techniques have become very popular in the in-circuit test industry, however for this technique to be viable, the in-circuit test platform requires electrical access to the component pins that are being tested.

Powered Opens is a recently developed test technique that combines boundary scan and vectorless technologies to create virtual access to PCB signal nets that may not have conventional test point access.

With this technique, a boundary scan device acts as an on-board stimulus generator while a capacitive sensor plate provides a means of detecting the resultant test signal.

This is an exciting new technique because it can detect continuity defects between boundary scan based ICs and other devices, including non-boundary scan devices, connectors, and sockets that lack physical test access defects that otherwise would escape traditional boundary scan and I.C.T. test methods.

One implementation, called Power Framescan, employs a novel set of time domain auto-correlation and cross-correlation algorithms that eliminate many of the restrictions associated with existing frequency domain alternatives.

More specifically, this test method does not place restrictions on the operating frequency of the boundary scan's clock signal or the number of scan cells in the boundary scan chain.

Analyzing the temporal response of a single event pulse in the time domain by use of matched filtering eliminates the need to generate the narrow range of stimulus frequencies that traditional capacitive sensor plate methods require. This virtual test method works with any boundary scan device that complies with the I.E.E.E. 1149.1, 1149.4 or 1149.6 standards.

Summary


Increased pressures to reduce time to market and time to volume have forced many manufacturers of populated printed circuit boards to rely on capacitively coupled, un-powered, vectorless in-circuit test techniques to identify open pins on ICs and connectors. Unfortunately, faster signals and higher-density printed circuit boards (PCBs) have placed pressures on designers to reduce the number of test pads that provide electrical access for vectorless test techniques.

A powered-up test solution using boundary scan as the stimulus generator and a capacitive sensor plate for detection can address this loss of access. This virtual access method can quickly and effectively identify connectivity defects between boundary scan based ICs and other devices, including non-boundary scan devices, connectors, and sockets that lack physical test access.

This test approach employs a novel set of time domain auto-correlation and cross-correlation algorithms that eliminate many of the restrictions associated with existing frequency domain alternatives. More specifically, this test method does not restrict the operating frequency of the boundary scan's clock signal (TCK) or the number of scan cells in the boundary scan chain. Analyzing the temporal response of a single event pulse in the time domain by use of matched filtering eliminates the need to generate the narrow range of stimulus frequencies that traditional capacitive sensor plate methods require.

This virtual test method works with any boundary scan device that complies with the IEEE 1149.1, 1149.4 or 1149.6 standards. A discussion of this test method as well as recent field data, lessons learned and obstacles overcome while implementing this technique on a high-end computer server product at a high volume production facility are disclosed.

Conclusions


Powered opens allows for virtual access on high density PCB assemblies where there is limited board real-estate for test pad access and on high speed PCB signals that cannot tolerate the negative effects of electrical test pads.

Matched filtering from cross correlation offers the maximum possible signal to noise ratio in a noise-prone powered up environment and minimizes the opportunity for false calls on the production line. Production data from LGA1366 sockets on server boards confirms that the pulse based test method is very capable in terms of noise immunity, throughput, repeatability and false call rate.

When using time domain edge analysis instead of the more traditional frequency domain analysis, there are no restrictions on the number of scan cells in the chain. As a result, the time domain technique can identify common process defects and is compatible with present and future boundary scan compliant silicon devices.

Initially Published in the IPC Proceedings

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