Electronics Assembly Knowledge, Vision & Wisdom
Stencil Printing Process Tools for Miniaturization
Stencil Printing Process Tools for Miniaturization
This paper offers preliminary test results relating to the stencil coating technology and how they impact miniaturization and high yield processing.
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Authored By:
Clive Ashmore & Mark Whitmore
DEK Printing Machines Ltd
Weymouth, Dorset, UK

Transcript
The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged.  

Miniaturization raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next to large for high mix technology assemblies? How closely can we place components for high density products?  

And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process? 

Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process.  

For next generation components and assembly processes these established rules need to be broken!  

New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation CSP technology.  

Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process.  

This paper offers preliminary test results relating to the stencil coating technology and how they impact miniaturization and high yield processing.

Summary
The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged.

Miniaturization raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place components for high density products? And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process!

Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For next generation components and assembly processes these established rules need to be broken!

New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation 0.3CSP technology. Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise.

In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process. Preliminary test results relating to the stencil coating technology and how they impact miniaturization and high yield processing will be presented.

Conclusions
This investigation has found that the inclusion of a Nano coating has dramatically reduced the propensity towards wet bridging. To ensure the Nano coatings efficiency was validated during the test, a test strategy was chosen to yield wet bridging.

Therefore the wet bridging results from the untreated stencil we re expected, although the untreated stencil did clearly show how one failure mode (wet bridge) can morph into an alternative failure (under stencil contamination).

The results from the treated stencil showed that even under a harsh test strategy a Nano coating inhibited wet bridging on 0.3mm pitch devices. This evidence verifies that the barrier created by the Nano technology has overcome the issues associated with a high squeegee filling pressure and stencil to board gasket violations.

The overall outcome from this test is one in which the process engineer has the ability to extend the number of print between under stencil cleans. This benefit is twofold:
* Increased throughput as a consequence of reduced cleaning.
* Reduced costs through decreased consumable consumption.

Initially Published in the IPC Proceedings

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