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Flip Chip Package Qualification
Flip Chip Package Qualification
Paper reviews solder interconnects on interposer substrates, X-ray and cross-sectional analysis of packages and process optimization efforts to improve reliability.
Materials Tech

Authored By:
Mumtaz Y. Bora
Peregrine Semiconductor
San Diego, CA USA
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Transcript
Quad Flat Pack No Leads are thermally enhanced plastic packages that use a conventional copper lead-frame with wire bonded interconnects. These leadless components provide an advanced packaging solution that reduces board real estate, with improved electrical and thermal performance over traditional leaded packages.

The move towards finer pitch is resulting in using flip chip bumps as interconnects on an interposer substrate. Successful assembly yields and solder joint reliability requires careful selection of substrate materials, fluxes, component plating finishes, controlled reflow processes and flatness of package and printed board.

Reflowing packages with flip chip bump interconnects requires a good balance of substrate /package material sets and controlled reflow profiles to ensure proper melt of the bump interconnects and solder joint reliability thru subsequent reflow processes at assembly facilities.

This paper reviews the qualification efforts for solder interconnects on interposer substrates, X-ray and cross-sectional analysis of packages and process optimization efforts to improve reliability of the interconnects.
Summary
Quad Flat Pack No Leads (QFNs) are thermally enhanced plastic packages that use conventional copper leadframe with wire bonded interconnects. . These leadless components provide an advanced packaging solution that reduces board real estate, with improved electrical and thermal performance over traditional leaded packages. The move towards finer pitch is resulting in using flip chip bumps as interconnects on an interposer substrate and packaging as QFN. [1]

The QFN devices commonly known as BTC (bottom terminated components) are attractive due to their low cost per I/O, performance and low profile; they are also a challenge for assembly due to their low to zero standoff height. Successful assembly yields and solder joint reliability requires careful selection of substrate materials, fluxes, component plating finishes, controlled reflow processes and flatness of package and PWB. [2]

This challenge is enhanced with the transition to lead free reflow as the higher peak reflow temperatures results in more thermal and CTE mismatch between package and PWB. Wire bonded leadframe packages are typically plated with 100% Matte tin or NiPdgold on the solderable terminations. Interposer substrate is typically plated with Electroless nickel /gold for solderability of terminations. War page characteristics of interposer substrates have to be evaluated to minimize stress on the flip chip bumps.

Reflowing packages with flip chip bump interconnects requires a good balance of substrate /package material sets and controlled reflow profiles to ensure proper melt of the bump interconnects and solder joint reliability thru subsequent reflow processes at assembly facilities.

The paper reviews the qualification efforts for solder interconnects on interposer substrates, X-ray and X-sectional analysis of packages and process optimization efforts to improve reliability of the interconnects
Conclusions
Bumped interconnects are a reliable form of interconnect if reflow process, mold material sets, substrate pads and solder mask are optimized. This will minimize CTE mismatch failures, dewetting of the bump and cracks at the bump to substrate interface. Solder bumps have the ability to self centre during reflow which minimizes failure due to misplacement. Package integrity can be maintained by proper control of processes.
Initially Published in the IPC Proceedings
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