Electronics Assembly Knowledge, Vision & Wisdom
Coreless Package Substrate Issues and Challenges
Coreless Package Substrate Issues and Challenges
This paper addresses the major challenges of reducing coreless substrate warpage in terms of both substrate manufacturing and assembly process.
Production Floor

Authored By:
Jinho Kim, Seokkyu Lee, Jaejun Lee
Seungwon Jung, Changsup Ryu
Unit Process Development of Advanced Circuit Interconnect
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Coreless technology in package substrate has been developed to satisfy the increasing demand of lighter, smaller and superior electrical performance regarding as the future trend in electronic application. However, there are major challenges of reducing coreless substrate warpage in terms of both substrate manufacturing and assembly process. Substrate manufactures typically provide substrate warpage within satisfying customer's specification which does not allow much margin left in assembly considering the number of reflows and curing profiles which the package undergoes during assembly.

However, it is very difficult to provide satisfying this level of warpage because coreless substrate is one-third as thin as conventional one and does not use stiff core material. The key element for success in coreless technology is to solve the warpage issue at manufacturing site because the decrease of bare substrate warpage is important to improve the assembly yield. To figure out these problems, design optimization, mechanical/thermal treatment and low CTE material are suggested in this study. Final part discusses assembly result and issue for future work.
Coreless package substrate offering advantages in terms of electrical performance, fine pattern/pitch and thin substrate has been developed. The key element to success with coreless technology is to solve the warpage issue in terms of both manufacturing and assembly process.

In this study, the authors pointed out three technologies to reduce the warpage, 1) design optimization 2) thermal/ mechanical treatment 3) low CTE materials. When all technologies are applied, the average warpage meets our goal. All warpage reduction technologies represented in this study show great effort. Even if bare substrate warpage is satisfied with customer's need, coreless substrates might have issues for package warpage during the assembly process. As increasing substrate size and die size, assembly and reliability of coreless package are more challenging.

In near future, it is necessary to develop coreless package in terms of package size, device size, substrate thickness and composition, mold encapsulant material, die attach thickness and material. The coreless technology into volume production today has not always been an easy road. However, we expect that the effort to understand coreless substrate such as bi-metal theory, CTE balanced structure and minimizing mechanical/thermal stress mentioned in this study will help to overcome these barriers.
Initially Published in the IPC Proceedings
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