Authored By:
Vern Solberg
STC-Madison
Madison, Wisconsin USA
Summary
The motivation for developing higher density IC packaging continues to be the market and the consumers' expectation that each new generation of products furnish greater functionality. The miniature IC package evolution began with the development of chip-scale and die-size package technology. These miniature IC package innovations proved ideal for portable and hand-held electronic applications. To address the need for even more functionality without increasing their products size, a number of companies have adapted various forms of multiple-die 3D packaging.
A majority of these early multiple function devices relied on the sequential stacking of die elements onto a single substrate interposer. Because the wire-bonding of multiple tiers of uncased die is rather specialized and the die used may have had relatively poor wafer level yields or were not always available in a pre-tested (KGD) condition, overall manufacturing yield of the stacked-die packaged devices have not always met acceptable levels. A key advantage of the package-on-package process is that each layer of the package can be pre-tested before joining. This capability greatly improves the overall manufacturing yield and the functional reliability of the final package assembly is assured. The information furnished in this paper will focus PoP package standards,, substrate design criteria and assembly methodology for efficient in-line assembly processing of vertically stacked IC package elements.
Conclusions
Package-on-Package technology has proved to be a practical solution for a number of high-performance, system-level applications. Whether the IC package sections are manufactured within a closed (in-house) environment or supplied from outside sources, quality and integrity of the end product is paramount. However, source and configuration control and material tracking throughout the life of the product are also a concern. Because each package section of the PoP component has been electrically tested before PCB mounting, the user can be assured that the multiple die products will meet all performance criteria without compromise. Even when IC package sections are furnished by differing offsite suppliers, the logic device supplier is responsible for assembly and test for the logic section, and the memory manufacturers will be responsible for assembly and testing of the respective memory section.
In regard to future applications, because the μPILR package enables a much finer pitch, a significantly higher number of contacts can be provided on both upper and lower package sections without increasing package size. In addition, the package assembly process utilizes an existing and mature manufacturing infrastructure allowing technology transfer to multiple sources of supply. In regard to package reliability, the μPIL R package structure has demonstrated excellent board-level durability, meeting or exceeding industry recognized thermal cycle and drop-shock requirements for lead-free soldering without using underfill or other reinforcement methods.
Because PoP designs are becoming more complex and the number of PoP interconnects between top and bottom packages are increasing, there is a growing demand for finer pitch PoP technologies capable of delivering 0.4mm or even 0.3mm pitch. There are limited options available that can meet this demand, but a growing number of semiconductor and OEM companies have concluded that the μPILR PoP is one such solution.
Initially Published in the IPC Proceedings
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