Electronics Assembly Knowledge, Vision & Wisdom
Reliability & Failure Mechanisms of Substrates
Reliability & Failure Mechanisms of Substrates
Paper surveys via related laminate failures using data from thermal cycling testing, failure analysis, and other sources.
Materials Tech

Authored By:
Kevin Knadle
Endicott Interconnect Technologies, Inc.
Endicott, NY USA
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Summary
The plated thru hole has changed considerably in 50 years of electronic packaging, but in its many forms remains the most common interconnection in 1st and 2nd level electronic packaging, and is still one of the most feared in terms of reliability. The transition from the original solder filled holes to BGA wiring vias, subcomposite buried vias, and today's microvias has resulted in many new failure mechanisms, not only in the copper interconnections but also in the surrounding laminate, especially with Pb free reflows.

This presentation surveys the most significant via and via-related laminate failure mechanisms from past to present using data from current induced thermal cycling (CITC) testing, failure analysis, and other sources. The relative life and failure modes of thru vias, buried vias, and microvias (stacked vs. non-stacked) are compared, along with the affect of structure, materials,and peak temperatures on the above.

The origin of via-induced laminate failures such as "eyebrow cracks" and Pb free related internal delamination is also explored. Video clips of laminate coupons during Pb free reflows are shown, including examples of failure mechanisms as they occur, to vividly illustrate the challenges involved and to help reveal the root causes. Finally, an extrapolation to future technology trends for laminate substrates is attempted to address the question-what might be the failure modes of tomorrow, and will via/laminate reliability be better or worse?
Conclusions
The complexity of laminate electronic packaging in terms of design, build, and reliability evaluation has reached a level today never imagined when the first PTH was filled with solder over 50 years ago. Today the design and process engineers have to deal with thru vias, microvias, buried vias, and Z-interconnect, each of which can be used blind or buried, composite or subcomposite, filled or unfilled, capped or uncapped, stacked or unstacked, and assembled with either SnPb, MSA , or Pb free solders.

Then quality and reliability has to be assured with a seemingly infinite mix of potential failure mechanisms that can occur either in the vias or induced by the vias in the surrounding laminate depending on the above design mix, process choices, and even last digit of the optimized peak assembly temperature. The successful user of this technology, today and tomorrow, will be those that neither over-react nor under-react, but recognize that:

1. The comfortable qualification margins of past product may longer be possible with today's HDI designs and Pb free reflows- reflow and via life requirements may need to be tailored for a specific product with the smart and innovative use of coupon tests.

2. Thorough evaluation and rigorous monitoring of products will become even more important given these margins.

3. "Design for reliability" is now as important as design for electrical and wiring needs, balancing the potential risks of via failure versus laminate failure based on material choice, via size and grid, and mix of thru vias versus compliant HDI structures
Initially Published in the IPC Proceedings
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