Electronics Assembly Knowledge, Vision & Wisdom
Is There a Passive Component Solder Void Limit?
Is There a Passive Component Solder Void Limit?
Is there a quality criteria for solder voids in passive components. Phil Zarrow and Jim Hall point to the answers.
Board Talk

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Board Talk is presented by ITM Consulting

Phil Zarrow
Phil Zarrow, ITM Consulting
With over 35 years experience in PCB assembly, Phil is one of the leading experts in SMT process failure analysis. He has vast experience in SMT equipment, materials and processes.

Jim Hall
Jim Hall, ITM Consulting
A Lean Six-Sigma Master Blackbelt, Jim has a wealth of knowledge in soldering, thermal technology, equipment and process basics. He is a pioneer in the science of reflow.

ITM Consulting
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Welcome to Board Talk. We are the Assembly Brothers, Phil Zarrow and Jim Hall of ITM Consulting, we're here to answer your questions on SMT processes, equipment, materials, and procedures. What is in our mailbag today, Jim?

Today we hear from HM. "I know about voids in BGA solder joints, but is there a quality criteria for the solder voids in passive components, including resistors, capacitors, etc.?"

When it comes to specifications, we always refer to IPC 610. In IPC 610 in Section 5.2.2 called Solder Anomalies, it talks about pinholes and blowholes, but also addresses voids. It defines a defect for Class II and Class III products as pinholes, blowholes, or voids which reduce the connection below the minimum requirements.

The requirements for chip components, resistors and capacitors is given in IPC 610 in Section 8.2.2. There are many different categories, but they talk basically about coverage on the pads and on the terminations and a number of them give percentages.

So theoretically, according to IPC, you could measure the void. If it's an internal void you'll need to use an x-ray machine. If it's an external void such as a blowhole, you could just measure it with a microscope. And then you could apply that to the joint category such as 50% coverage, 75% coverage, and so forth that are listed in the 8.2.2 sections.

These measurements are theoretically possible, but they are typically judgment calls.

When we look at these specs, we're basically comparing contact area voids with things like mis-alignments, skewed components, things along those lines.

Say you had a void near the toe of a solder fillet and the spec says that you need to have less than 75% coverage. So you look at the coverage and if a void was bigger than 25%, that would reduce your total to less than 75%.

That's easy to say here quoting numbers off the top of our heads, but I think in real life, it's subjective. But to answer your question, yes, there are criteria and they are defined in the IPC.

The trick is to determine if voids are a symptom or a defect, particularly before you go about doing any actual reworking and manipulation where you could do more harm than good.

That initial spec, 5.2.2, defines all voids, blowholes, and pinholes as a process indicator. So if you're seeing them, they're telling you that maybe there's something wrong. Whether a specific one causes you to reject a part or rework it is often a judgment call against the criteria in 8.2.2.

That's about it for today's Board Talk. For Board Talk, this is Phil Zarrow and Jim Hall saying goodbye and remember, whatever you do ...

Don't solder like my brother.

Please don't solder like my brother.

Watch out for those voids.

Reader Comment

Defects are caused by imperfect processes, equipment and materials. Many factors create issues where cost of getting better results out weigh the gain in profit. Every solder joint should be perfect! We accept less because a document says we can. Hence, the Classes of "Acceptable"! An imperfect product only impacts your customer and their impression of your business. It's your choice to succeed or fail. Now, what would you consider acceptable? There is a lot of talk about voids- but a component 25% or more skewed off the pad is acceptable.

Question: Will this impact the purchasers or end users life in any way? Cost of producing a less expensive product results in defects. Better process controls and materials result in better products, sales and add more to the bottom line. Less defects = less troubleshooting, less repair or rework. Take that cost away and add it to the front end of producing the best product you can. If you don't someone else will. Get to root causes. Improve your process and take another look at this voiding issue. Hint (voids) - Process thermals, materials used and times in the process stages.

Mark A. Maheux Sr., Honeywell
Reader Comment

I just took a look into latest IPC-A-610F standard (July 2014)and yes indeed in Section 5.2.2 called Solder Anomalies, it do addresses voids, but in Section 8.2.2 no requirements for voids percentage whatsoever for chip components, resistors and capacitors is mentioned!!

This is the actual quote of 8.2.2 section from IPC-A610F standard:

"8.2.2 SMT Leads - Damage, These criteria are applicable whether leads are formed manually or by machine or die.

Acceptable - Class 1,2,3
  • No nicks or deformation exceeding 10% of the diameter, width or thickness of the lead. See 5.2.1 for exposed basis metal criteria.
Defect - Class 1,2,3
  • Lead is damaged or deformed more than 10% of the diameter, width or thickness of the lead.
  • Lead is deformed from repeated or careless bending.
  • Heavy indentations such as serrated pliers mark."
Can you please elaborate more in which IPC 610 version, section 8.2.2 is defining pass/fail criteria for passive components?

Dr. Avi Rochman, Flex
Reader Comment

As Jim and Phil describe, this topic has a lot of factors. Specification interpretation is mentioned as a challenging variable as all sources of data are not consistent. Materials involved, types and grade of components used, vendors and solder types to name a few are relevant to failure modes and acceptable factors of safety. If the component breaks before the solder joint, it seems this should be relevant.

One commenter mentioned views about 25% voiding - is this data supported by reliability testing? I have customers who allow up to 40% for such devices. We know a lot about BGA devices and related long term life testing. I have had limited success finding information on this topic for small body SMT devices that are supported by actual reliability data.

I would be interested if you or anyone knows of actual testing that helps confirm or support the limits described in IPC-610 section 8.2.2, registration and voids effects on small package SMT devices. End user industry feedback and reliability experts I have consulted describe larger body sizes as having more serious, adverse effects related to voids, cracking due to CTE mismatches and the related mechanical stresses.

My interest and information is specific to 0402 body size components. They have very low mass, small foot print area and appear to be very robust when scale is accounted for. We used type 2 acceptance criteria for solder spec definitions. In parallel, we did create, where possible beyond those limits as part of our boundary definitions testing.

As part of a product qualification plan, we limited ourselves to comparing 0402 100nF ceramic X7R capacitors from 2 different, high end capacitor manufactures. We tested devices on PCBs and simultaneously in our products. We studied some of the effects of solder voiding. We applied the same number of samples with 0402 Null ohm resistors in parallel testing platforms. This standard test could measure all joints for low level resistance changes in addition to the parameters we wished to cover ( LLCR = < 10 milliohm max delta. Solder joints usually start to show resistive changes above ~90--> 100 milliohms). We continuously monitored Capacitance and Resistance (LCR bridge meter - Cs and Rs component levels ) changes on the DUT that had the 0402 capacitors on board.

We compared effects of voiding, co planarity and pad registration effects. We mounted 0402 caps in our product and on to PCB surfaces using industry standard land definitions per customer directives. The board material was a standard FR4 material.

Solder attach was a lead free Bi/Sn/Ag, low temperature attach due to material high end temp limit constraints.

We used multiple accelerated testing effects in over 2,500 solder joints. Shock (>200 G drop tests), Accelerated Thermal Cycle( 0-100 Deg C 2 Deg / min ramp - 10 min dwells -> 1,500 cycles), Biased Humidity 85c/85% RH, bend testing related to our product, over mating, rework cycles and thermal age tests.

We set certain test boundaries beyond expected use to look for boundary conditions as voiding, registration, conformal coating effects, board bow, twist etc are all involved in long term reliability.

With regard to voiding, we built some test groups with 30, 40 and > 50% voiding. Component to pad Registration was all very good - both on the board and on our product - it was difficult to create registration defects when you seem to want to on the board or on our product.

X ray, PDA / cross section, LLCR, die and pry analysis all suggested that even at beyond 50 % voiding, 0402 product size component will survive environmental acceleration testing with no measurable adverse effects.

We did create failures when pushed components beyond rated capabilities of the components used or beyond our process control limits. We had multiple Board level failures, but zero at the solder joint level.

Handling damage of components onto the boards was the main culprit, although some small percentage of the Null Ohm resistors failed as we did significant testing beyond rated limits.

Our conclusion based upon our testing, voiding did not play a statistically relevant factor until we went beyond 50% volume defined by 2D X ray and die and pry results. Solder joints all survived - internal component damage was identified as root cause for cases not damaged due to handling.

If readers have test data that supports the IPC board level specification components for these types of devices I would be interested in hearing about the results.

Best Regards.

Don Girard, Amphenol-TCS
Reader Comment

S.A. you are certainly on the right track.

The significance of a void is directly related to its location in the solder joint, vertical as well as horizontal.

You use a 5DX, so you can determine vertical position relatively
accurately and (hopefully) repeatably. If everyone had a 5DX or
comparable tool, we (IPC etc) could start to define a spec based on 3-D void locations co-related to solder joint reliability data. But most assembler's don't have access to this kind of inspection tool.

Enough of the industry utilizes top-down X-Ray such that most can measure horizontal area of voids within a joint. As we stated in Board Talk, we don't feel that it is a very useful spec, INemi has test data that refutes the 25% horizontal criteria.

The current reality is that individual users such as yourself, will have to struggle with the tools you have available and establish your own co-relations between measured void data and the reliability requirements of your products, leading to in-house acceptance criteria.

Thank you for your feedback and sharing your experience.

James Hall, ITM Consulting
Reader Comment

This was very interesting to me due to the fact that some have been saying with Rev. D of the 610 that voiding is just a process indicator. I have never agreed with that because I knew that a void was missing solder and would weaken the solder joint.

I program an Agilent 5DX. My major concern are voids in the heels of FPGs. When I teach operators I say that I would personally fix any void larger that 25% in the heel, but they should follow the direction of their Quality Engineer.

I looked at a 610 version from Feb 2005 section 5.2.2 and it did mention voids being a defect if the joint would not meet the solder specs. I would not have found it except for your article. Our solder criteria references ANSI/J-STD-001D. Most voiding topics deal with BGAs.

I did some internet research before our adoption if the version D and the industry appeared to be divided down the middle as far as voiding goes.

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