Electronics Assembly Knowledge, Vision & Wisdom
Design for Flip-Chip and Chip-Size Technology
Design for Flip-Chip and Chip-Size Technology
This paper provides a comparison of flip-chip and wafer level array package methodologies detailed in IPC-7094.
Materials Tech

Authored By:
Vern Solberg
Solberg Technology Consulting
Madison, Wisconsin
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Transcript

As new generations of electronic products emerge they often surpass the capability of existing packaging and interconnection technology and the infrastructure needed to support newer technologies.

The gap between printed boards and semiconductor technology (wafer level integration) is greater than one order of magnitude in interconnection density capability, although the development of fine-pitch substrates and assembly technology has narrowed the gap somewhat.

This paper provides a comparison of different commonly used technologies including flip-chip, chip-size and wafer level array package methodologies detailed in a new publication, IPC-7094.

It considers the effect of bare die or die-size components in an uncased or minimally cased format, the impact on current component characteristics and reviews the appropriate PCB design guidelines to ensure efficient assembly processing.

Summary
As new generations of electronic products emerge they often surpass the capability of existing packaging and interconnection technology and the infrastructure needed to support newer technologies. This movement is occurring at all levels: at the IC, at the IC package, at the module, at the hybrid, the PC board which ties all the systems together.

Interconnection density and methodology becomes the measure of successfully managing performance. The gap between printed boards and semiconductor technology (wafer level integration) is greater than one order of magnitude in interconnection density capability, although the development of fine-pitch substrates and assembly technology has narrowed the gap somewhat. All viable efforts are being used in filling this void utilizing uncased integrated circuits (flip-chip) and incorporating more than one die or more than one part in the assembly process.

This paper provides a comparison of different commonly used technologies including flip-chip, chip-size and wafer level array package methodologies detailed in a new publication, IPC-7094. It considers the effect of bare die or die-size components in an uncased or minimally cased format, the impact on current component characteristics and reviews the appropriate PCB design guidelines to ensure efficient assembly processing. The focus of the IPC document is to provide useful and practical information to those who are considering the adoption of bare die or die size array components.
Conclusions
Feature sizes for WLBGA and DSBGA packages will continue to shrink as the silicon fabrication technology adopts significantly higher circuit densities. This trend will allow the IC designer to further compress the functionality onto even smaller die outlines. To maintain the minimal finished package outline it will be necessary to reduce the contact size and move the contact features closer together. We can expect the next generation of these components to push the limits of printed circuit fabrication capability. In preparation for higher density circuit boards, designers and suppliers will need to work together in selecting the best laminate materials and adopt more advanced fabrication processes.

Even today, the higher density circuit routing and contact features are very near the size of early semiconductor technology, prompting circuit fabrication specialist to employ more sophisticated clean-room enclosures around key processes. For example, any microscopic particles at any stage of the circuit fabrication environment will have the potential to cause fatal defects.

The photo-lithographic process steps in particular and the preparation steps leading up to the process are particularly vulnerable to particle contamination. Additionally, surface contamination or incompatible surface finish on the substrate is a concern because they can potentially contribute to product failure. In regard to market acceptance and performance of WLBGA and DSBGA technology, there remain significant challenges that need to be addressed:

•Aggressive cost reduction strategies
•Consistency of die level quality
•Refining wafer and component level test capability
•PCB design analysis and assembly modeling capabilities
•Reliability improvement strategies

In regard to package and module assembly, there will be an ongoing need for the OEM or EMS provider to make capital improvements to their facility. Improvements in the form of a cleaner environment for each process and significantly greater accuracy in solder print ing, device placement and solder process control.
Initially Published in the IPC Proceedings
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