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These programs cover bare PC board fabrication, circuit board design, laminates and more. Programs are sorted by published date, most recent first.
Can a CTE Mismatch Cause Reliability Problems?
Does usage of BGAs, QFNs or SONs have an increased risk for reliability of solder joints due to the CTE mismatch with the base board material FR4? Jim Hall and Phil Zarrow, The Assembly Brothers, offer their own experiences.
Challenges on ENEPIG Finished PCBs
Through extensive investigation, using 8D and Kepner-Tregoe problem solving methods, solutions were discovered in the majority of cases.
Effect of Assembly Pitch and Distance on Solder Joint Thermal Cycling Life
Cycles-to-failure versus Distance to Neutral Point (DNP) data for SnPb and lead-free assemblies under Accelerated Thermal Cycling (ATC) conditions are observed.
Insertion Loss Comparisons of High Frequency PCBs
PCBs have been used for many years in low loss, high frequency microwave applications and many have become increasingly complex.
Realization of a New Concept for Power Chip Embedding
This paper will focus on the behavior of the power module for operational conditions of a PedEleC (Pedal Electric Cycle) application.
Help With Lead to Hole Ratio
What is the proper minimum gap between a round conductor lead and the PCB hole that will allow proper solder fill? Where can I find the recommended guideline?
Influence of Copper Conductor Surface Treatment for High Frequency PCB
Paper provides results of adhesion performance and electrical properties using certain types of dielectric material for high frequency PCBs.
V-Score and Depanel in One Step
Can we score and de-panel assembled PCBs in one step to create a card edge connector on the PCB. Is there a precedence for doing this? Jim Hall and Phil Zarrow, The Assembly Brothers, answer this question.
BTC-QFN Test Board Design for Qualifying Soldering Materials
This research uses a non-standard test board with sensors placed at the bottom termination to study cleanliness and contamination effects under QFN components.
Board Level Failure Analysis Demount Challenges Package Package
Board level FA and component demount experiments for PoP mounted on PCB is discussed. The FA methods includes 2D and 3D X-ray imaging, cross section and DnP test.
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